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1 ? HI5741 14-bit, 100msps, high speed d/a converter the HI5741 is a 14-bit, 100msps, d/a converter which is implemented in the intersil b icmos 10v (hbc-10) process. operating from +5v and -5.2v, the converter provides 20.48ma of full scale output current and includes an input data register and bandgap volt age reference. low glitch energy and excellent frequency domain performance are achieved using a segmented arch itecture. the digital inputs are ttl/cmos compatible and tr anslated internally to ecl. all internal logic is implemented in ecl to achieve high switching speed with low noise. the addition of laser trimming assures 14-bit linearity is maintained along the entire transfer curve. features ? throughput rate . . . . . . . . . . . . . . . . . . . . . . . . 100msps ? low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mw ? integral linearity error . . . . . . . . . . . . . . . . . . . . . . . 1 lsb ? low glitch energy . . . . . . . . . . . . . . . . . . . . . . . . . . 1pv-s ? ttl/cmos compatible inputs ? improved hold time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns ? excellent spurious free dynamic range ? pb-free plus anneal available (rohs compliant) applications ? cellular base stations ? wireless communications ? direct digital frequency synthesis ? signal reconstruction ? test equipment ? high resolution imaging systems ? arbitrary waveform generators pinout HI5741 (28 ld soic) top view ordering information part number part marking temp. range (c) package pkg. dwg. # HI5741bib HI5741bib -40 to +85 28 ld soic m28.3 HI5741bib-t HI5741bib 28 ld soic tape and reel m28.3 HI5741bibz (note) HI5741bibz -40 to +85 28 ld soic (pb-free) m28.3 HI5741bibz-t (note) HI5741bibz 28 ld soic tape and reel (pb-free) m28.3 HI5741-evs +25 evaluation board (soic) note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d13 (msb) d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dgnd ref out ctrl amp out ctrl amp in r set i out artn dv ee dgnd dv cc clock agnd av ee i out data sheet september 20, 2006 fn4071.12 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2000, 2001, 2003, 2004, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn4071.12 september 20, 2006 typical application circuit functional block diagram d11 (3) d10 (4) d9 (5) d8 (6) d7 (7) d6 (8) d5 (9) d4 (10) d11 d10 d9 d8 d7 d6 d5 d4 +5v dv cc (16) 0.01 f dgnd (17, 28) clk (15) -5.2v (av ee ) 0.1 f (19) artn (22) av ee d/a out (21) i out (20) i out (23) r set 976 ? 64 ? (24) ctrl amp in HI5741 d12 d13 d13 (msb) (1) d12 (2) dv ee (18) -5.2v (av ee ) 0.01 f (25) ctrl amp out (26) ref out 64 ? 0.1 f -5.2v (dv ee ) 0.01 f 0.1 f (27) agnd 50 ? d3 (11) d2 (12) d3 d2 d1 (13) d1 d0 (lsb) (14) d0 upper slave i out (lsb) d0 d1 d2 d3 d4 d5 d6 d9 d7 d8 4-bit decoder r2r network i out + - ctrl amp ref out r set ctrl amp 25 ? 14-bit master register out 15 switched current cells 10 lsbs current cells d10 (msb) d13 register data buffer/ level shifter overdriveable voltage reference in clk ref cell d11 d12 227 ? 227 ? av ee agnd dv ee dgnd dv cc 15 15 artn HI5741
3 fn4071.12 september 20, 2006 absolute maximum ratings t a =+25c thermal information digital supply voltage v cc to dgnd . . . . . . . . . . . . . . . . . . . +5.5v negative digital supply voltage dv ee to dgnd . . . . . . . . . . -5.5v negative analog supply voltage av ee to agnd, artn . . . . -5.5v digital input voltages (d13-d0, clk) to dgnd. . . . . dv cc to -0.5v internal reference output current. . . . . . . . . . . . . . . . . . . . 2.5ma voltage from ctrl amp in to av ee . . . . . . . . . . . . . . . . 2.5v to 0v control amplifier output current . . . . . . . . . . . . . . . . . . . . . 2.5ma reference input voltage range. . . . . . . . . . . . . . . . . -3.7v to av ee analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 30ma operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, note 1) ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature HI5741bix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications av ee , dv ee = -4.94v to -5.46v, v cc = +4.75 to +5.25v, v ref = internal, t a = +25c parameter test conditions HI5741bi t a = -40c to +85c units min typ max system performance resolution 14 - - bits integral linearity error, inl (note 5) ?best fit straight line?, t a = +25c -1.5 1.0 1.5 lsb ?best fit straight line?, t a = -40c to +85c -1.75 - 1.75 lsb differential linearity error, dnl (note 5) t a = +25c -1.0 0.5 1.0 lsb offset error, i os (note 5) - 8 75 a full scale gain error, fse (notes 3, 5) - 3.2 10 % full scale gain drift with internal reference - 150 - ppm fsr/c offset drift coefficient (note 4) - - 0.05 a/c full scale output current, i fs - -20.48 - ma output voltage compliance range (note 4) -1.25 - 0 v dynamic characteristics throughput rate (note 4) 100 - - msps output voltage settling time ( 1 / 16 th scale step across segment) r l = 64 ? (note 4) - settling to 0.024% - 11 - ns r l = 64 ? (note 4) - settling to 0.012% - 20 - ns singlet glitch area, ge (peak) r l = 64 ? (note 4) - 1 - pv?s output slew rate r l = 64 ?, dac operating in latched mode (note 4) - 1,000 - v/ s output rise time r l = 64 ?, dac operating in latched mode (note 4) - 675 - ps output fall time r l = 64 ?, dac operating in latched mode (note 4) - 470 - ps spurious free dynamic range within a window (note 4) f clk = 10 msps, f out = 1.23mhz, 2mhz span - 87 - dbc f clk = 20 msps, f out = 5.055mhz, 2mhz span - 77 - dbc f clk = 40 msps, f out = 16mhz, 10mhz span - 75 - dbc f clk = 50 msps, f out = 10.1mhz, 2mhz span - 80 - dbc f clk = 80 msps, f out = 5.1mhz, 2mhz span - 78 - dbc f clk = 100 msps, f out = 10.1mhz, 2mhz span - 79 - dbc HI5741
4 fn4071.12 september 20, 2006 spurious free dynamic range to nyquist (note 4) f clk = 10 msps, f out = 1.023mhz, 5mhz span - 86 - dbc f clk = 10 msps, f out = 2.02mhz, 5mhz span - 85 - dbc f clk = 25 msps, f out = 2.02mhz, 12.5mhz span - 77 - dbc f clk = 50 msps, f out = 5.055mhz, 25mhz span - 74 - dbc f clk = 75 msps, f out = 7.52mhz, 37.5mhz span - 73 - dbc f clk = 100 msps, f out = 10.1mhz, 50mhz span - 71 - dbc multi-tone power ratio (mtpr) 8 tones, no clipping, 110kh z spacing, 220khz spacing between tones 4 and 5, f clk = 20 msps (note 7) -76-dbc reference/control amplifier internal reference voltage, v ref (note 5) -1.27 -1.23 -1.17 v internal reference voltage drift (note 4) - 50 - v/c internal reference output current sink/source capability (note 4) -500 - +50 a internal reference load regulation i ref = 0 to i ref = -500 a - 100 - v amplifier input impedance (note 4) - 3 - m ? amplifier large signal bandwidth 4.0v p-p sine wave input, to slew rate limited (note 4) - 1 - mhz amplifier small signal bandwidth 1.0v p-p sine wave input, to -3db loss (note 4) - 5 - mhz reference input impedance (ctl in) (note 4) - 12 - k ? reference input multiplying bandwidth (ctl in) r l = 50 ? , 100mv sine wave, to -3db loss at i out (note 4) -75-mhz digital inputs (d9-d0, clk, invert) input logic high voltage, v ih (note 5) 2.0 - - v input logic low voltage, v il (note 5) - - 0.8 v input logic current, i ih (note 5) - - 400 a input logic current, i il (note 5) - - 700 a digital input capacitance, c in (note 4) - 3.0 - pf timing characteristics data setup time, t su see figure 1 (note 4) 3 2.0 - ns data hold time, t hld see figure 1 (note 4) 0.5 0.25 - ns propagation delay time, t pd see figure 1 (note 4) - 4.5 - ns clk pulse width, t pw1 , t pw2 see figure 1 (note 4) 1.0 0.85 - ns power supply characteristics iv eea (note 5) - 42 50 ma iv eed (note 5) - 75 95 ma iv ccd (note 5) - 13 20 ma power dissipation (note 5) - 650 - mw power supply rejection ratio v cc 5%, v ee 5% - 5 - a/v notes: 2. dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. gain error measured as the error in the ratio between the full scale output current and the current through r set (typically 1.28ma). ideally the ratio should be 16. 4. parameter guaranteed by design or characterization and not production tested. 5. all devices are 100% tested at +25c. 6. dynamic range must be limited to a 1v swing within the compliance range. 7. in testing mtpr, tone frequencies ranged from 1.95mhz to 3.05m hz. the ratio is measured as t he range from peak power to peak distortion in the region of removed tones. electrical specifications av ee , dv ee = -4.94v to -5.46v, v cc = +4.75 to +5.25v, v ref = internal, t a = +25c (continued) parameter test conditions HI5741bi t a = -40c to +85c units min typ max HI5741
5 fn4071.12 september 20, 2006 timing diagrams figure 1. full scale settling time diagram figure 2. peak glitch area (singlet) measurement method figure 3. propagation delay, setup time, hold time and minimum pulse width diagram clk d13-d0 i out 50% t sett error band t pd v t(ps) height (h) width (w) glitch area = 1 / 2 (h x w) clk d13-d0 i out 50% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld t sett t sett t sett HI5741
6 fn4071.12 september 20, 2006 typical performance curves figure 4. typical power dissipation over temperature figure 5. typical reference voltage over temperature figure 6. typical inl performance figure 7. typical dnl performance figure 8. typical offset current over temperature figure 9. typical gain error over temperature 670 660 650 640 630 620 610 600 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) (mw) note: clock frequency does not alter power dissipation -1.17 -1.18 -1.19 -1.20 -1.21 -1.22 -1.23 -1.27 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) (v) -1.24 -1.25 -1.26 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0 5000 10,000 15,000 code (lsb) 0.8 0.5 0.25 0 -0.25 -0.5 -0.8 0 5000 10,000 15,000 code (lsb) 35 30 25 20 15 10 5 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) ( a) 40 4.2 2.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) (%) 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 HI5741
7 fn4071.12 september 20, 2006 figure 10. sfdr vs clock frequency fi gure 11. sfdr vs clock frequency figure 12. sfdr vs f out figure 13. sfdr vs f out figure 14. sfdr vs f out figure 15. harmonic distortion vs clock frequency typical performance curves (continued) 50 f clk (msps) 90 85 80 75 70 65 60 (dbc) 60 70 80 90 100 40 30 20 10 f out = ( 1 / 10 ) f clk 50 f clk (msps) 90 85 80 75 70 65 60 (dbc) 60 70 80 90100 40 30 20 10 f out = ( 1 / 5 ) f clk f out (msps) 82 80 76 68 66 64 62 (dbc) 10 5 1 74 72 70 f clk = 50 msps f out (mhz) 82 80 76 68 66 64 62 (dbc) 10 5 1 74 72 70 15 f clk = 75 msps 78 f out (mhz) 80 78 76 68 66 64 62 (dbc) 10 5 1 74 72 70 15 f clk = 100 msps 20 50 f clk (msps) -72 -74 -76 -78 -80 -82 -86 (dbc) 60 70 80 90100 40 30 20 10 -84 f out = 2.03mhz 3rd harmonic 2nd harmonic HI5741
8 fn4071.12 september 20, 2006 figure 16. typical mtpr performance figure 17. sfdr within a window figure 18. typical settling time performance figure 19. typical glitch energy pin descriptions pin no. pin name pin description 1-14 d13 (msb) thru d0 (lsb) digital data bit 13, the most signi ficant bit through digital data bit 0, the least significant bit. 15 clk data clock pin 100khz to 100 msps. 16 dv cc digital logic supply +5v. 17, 28 dgnd digital ground. 18 dv ee -5.2v logic supply. 23 r set external resistor to set the full scale output current. i fs = 16 x (v refout /r set ). typically 976 ? . 27 agnd analog ground supply current return pin. 19 artn analog signal return for the r/2r ladder. 21 i out current output pin. 20 i out complementary current output pin. 22 av ee -5.2v analog supply. 24 ctrl amp in input to the current source base rail. typically connected to ctrl amp out and a 0.1 f capacitor to av ee . allows external control of the current sources. 25 ctrl amp out control amplifier out. prov ides precision control of the current sources when connected to ctrl amp in such that i fs = 16 x (v refout /r set ). 26 ref out -1.23v (typical) bandgap reference voltage output. can sink up to 500 a or be overdriven by an external reference capable of delivering up to 2ma. typical performance curves (continued) start 1.900mhz s stop 3.100mhz 10db/ c f clk = 20 msps mtpr = 75.17dbc center 26.637mhz s span 2.000mhz 10db/ c f clk = 100 msps f out = 26.6mhz sfdr = 77.5dbc 1 ch1 1.00mv ~ m 5.0ns ch1 -16.9mv settling time ~ 10ns ? : 240 v @ : -30.96mv 12-bit window 1 ch1 1.00mv m 5.0ns ch1 -109mv glitch = (0.5) ? (300 v) ? (3.3ns) = 0.495pv/s ? : 300 v @ : -124.1mv HI5741
9 fn4071.12 september 20, 2006 detailed description the HI5741 is a 14-bit, current out d/a converter. the dac can convert at 100 msps and runs on +5v and -5.2v supplies. the architecture is an r/2r and segmented switching current cell arrangement to reduce glitch. laser trimming is employed to tune linearity to true 14-bit levels. the HI5741 achieves its low power and high speed performance from an advanc ed bicmos process. the HI5741 consumes 650mw (typical) and has an improved hold time of only 0.25ns (typical). the HI5741 is an excellent converter for use in communications applications and high performance video systems. digital inputs the HI5741 is a ttl/cmos compatible d/a. data is latched by a master register. once latched, data inputs d0 (lsb) through d13 (msb) are internally translated from ttl to ecl. the internal latch and switchi ng current source controls are implemented in ecl technology to maintain high switching speeds and low noise characteristics. decoder/driver the architecture employs a sp lit r/2r ladder and segmented current source arrangement. bits d0 (lsb) through d9 directly drive a typical r/2r network to create the binary weighted current sources. bits d10 through d13 (msb) pass through a ?thermometer? decoder that converts the incoming data into 15 individual segmented current source enables. this split architecture helps to improve glitch, thus resulting in a more constant glitch characteri stic across the entire output transfer function. clocks and termination the internal 14-bit register is updated on the rising edge of the clock. since the HI5741 clock rate can run to 100 msps, to minimize reflections and clock noise into the part, proper termination should be used. in pcb layout clock runs should be kept short and have a minimum of loads. to guarantee consistent results from board to board, controlled impedance pcbs should be used with a char acteristic line impedance z o of 50 ? . to terminate the clock line, a shunt terminator to ground is the most effective type at a 100 msps clock rate. a typical value for termination can be determined by the equation: for the termination resistor. for a controlled impedance board with a z o of 50 ? , the r t = 50 ? . shunt termination is best used at the receiving end of the transmission line or as close to the HI5741 clk pin as possible. rise and fall times and propagation delay of the line will be affected by the shunt terminator. the terminator should be connected to dgnd. noise reduction to reduce power supply noise, separate analog and digital power supplies should be used with 0.1 f and 0.01 f ceramic capacitors placed as close to the body of the HI5741 as possible on the analog (av ee ) and digital (dv ee ) supplies. the analog and digital ground returns should be connected together back at th e device to ensure proper operation on power up. the v cc power pin should also be decoupled with a 0.1 f capacitor. reduction of digital noise (caused by high slew rates on the bit inputs to the HI5741) can be accomplished through the use of series termination resistors. the use of serial resistors, which combine with the input capacitance of the HI5741 to induce a low pass filter characteristic, keeps the noise generated by high slew rate digital signals from corrupting the high accuracy analog data. refer to application note an9619 ?optimizing setup conditions for high accuracy measurements of the HI5741? for further details on selecting the proper value of series termination to meet application specific needs. reference the internal reference of the HI5741 is a -1.23v (typical) bandgap voltage reference with 50 v/c of temperature drift (typical). the internal reference is connected to the control amplifier which in turn drives the segmented current cells. reference out (ref out) is internally connected to the control amplifier. the control amplifier output (ctrl out) should be used to drive the cont rol amplifier input (ctrl in) and a 0.1 f capacitor to analog v ee . this improves settling time by providing an ac grou nd at the current source base node. the full scale output current is controlled by the ref out pin and the set resistor (r set ). the ratio is: i out (full scale) = (v ref out /r set ) x 16. the internal reference (ref out) can be overdriven with a more precise external reference to provide better performance over temperature. figure 21 illustrates a typical external reference configuration. r t z o = r t = 50 ? HI5741 dac clk z o = 50 ? figure 20. HI5741 clock line termination figure 21. external reference configuration (26) ref out HI5741 r -5.2v -1.25v HI5741
10 fn4071.12 september 20, 2006 multiplying capability the HI5741 can operate in two different multiplying configurations. for frequencies from dc to 100khz, a signal of up to 0.6v p-p can be applied directly to the ref out pin as shown in figure 22. the signal must have a dc value such that the peak negative voltage equals -1.25v. alternately, a capacitor can be placed in series with ref out if a dc multiplying is not required. the lower input bandwidth can be calculated using the following formula: for multiplying frequencies above 100khz, the ctrl in pin can be driven directly as seen in figure 23. the nominal input/output relationship is defined as: in order to prevent the full scale output current from exceeding 20.48ma, the r set resistor must be adjusted according to the following equation: the circuit in figure 23 can be tuned to adjust the lower cutoff frequency by adjusting capacitor values. table 1 illustrates the relationship. also, the input signal must be limited to 1v p-p to avoid distortion in the dac output current caused by excessive modulation of the internal current sources. outputs the outputs i out and i out are complementary current outputs. current is steered to either i out or i out in proportion to the digital input code. the sum of the two currents is always equal to the full scale current minus one lsb. the current output can be converted to a voltage by using a load resistor. both current outputs should have the same load resistor (64 ? typically). by using a 64 ? load on the output, a 50 ? effective output resistance (r out ) is achieved due to the 227 ? ( 15%) parallel resistance seen looking back into the output. this is the nominal value of the r2r ladder of the dac. the 50 ? output is needed for matching the output with a 50 ? line. the load resistor should be chosen so that the effective output resistance (r out ) matches the line resistance. the output voltage is: v out = i out x r out . i out is defined in the re ference section. i out is not trimmed to 14 bits, so it is not recommended that it be used in conjunction with i out in a differential-to-single-ended application. the compliance range of the output is from -1.25v to 0v, with a 1v p-p voltage swing allowed within this range. settling time the settling time of the HI5741 is measured as the time it takes for the output of the dac to settle to within a defined error band of its final value during a 1 / 16 th (code 0000... to 0001 0000.... or 1111... to 1110 1111...) scale transition. in defining settling time specificatio ns for the HI5741, two levels of accuracy are considered. the accuracy levels defined for the HI5741 are 12 (or 0.024%) and 13 (0.012%) bits. glitch the output glitch of the hi5 741 is measured by summing the area under the switching tran sients after an update of the dac. glitch is caused by the time skew between bits of the incoming digital data. typically, the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (ttl designs). unequal delay paths through the device can al so cause one current source figure 22. low frequency multiplying bandwidth circuit ref out HI5741 c in (optional) 0.01 f rset v in ctrl out ctrl in av ee c in 1 2 () 1400 () f in () ------------------------------------------- = figure 23. high frequency multiplying bandwidth circuit HI5741 ctrl in v in ctrl out av ee 200 ? c 2 c 1 50 ? ? i out ? v in 80 ? ------------- - = r set 16v ref i out full scale () v in peak () 80 ? ----------------------------- ?? ?? ? ----------------------------------------------------------------------------------------- - = table 1. capacitor selection f in c 1 c 2 100khz 0.01 f1 f >1mhz 0.001 f0.1 f table 2. input coding vs current output input code (d13-d0) i out (ma) i out (ma) 11 1111 1111 1111 -20.48 0 10 0000 0000 0000 -10.24 -10.24 00 0000 0000 0000 0 -20.48 HI5741
11 fn4071.12 september 20, 2006 to change before another. in order to minimize this, the intersil HI5741 employs an internal register, just prior to the current sources, which is updat ed on the clock edge. lastly, the worst case glitch on traditional d/a converters usually occurs at the major transitio n (i.e., code 8191 to 8192). however, due to the split architecture of the HI5741, the glitch is moved to the 1023 to 1024 transition (and every subsequent 1024 code transitions thereafter). this split r/2r segmented current so urce architecture, which decreases the amount of current switching at any one time, makes the glitch practically constant over the entire output range. by making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. in measuring the output glitch of the HI5741 the output is terminated into a 64 ? load. the glitch is measured at any one of the current cell carry (code 1023 to 1024 transition or any multiple thereof) througho ut the dacs output range. the glitch energy is calcul ated by measuring the area under the voltage-time curve. figure 25 shows the area considered as glitch when changing the da c output. units are typically specified in picovolt/seconds (pv/s). applications bipolar applications to convert the output of the hi 5741 to a bipolar 4v swing, the following applications circuit is recommended. the reference can only provide 125 a of drive, so it must be buffered to create the bipolar offset current needed to generate the -2v output with all bits ?off?. the output current must be converted to a voltage and then gained up and offset to produce the proper swing. care must be taken to compensate for the voltage swing and error. interfacing to the hsp45106 nco-16 the hsp45106 is a 16-bit numerically controlled oscillator (nco). the hsp45106 can be used to generate various modulation schemes for direct digital synthesis (dds) applications. figure 27 shows how to interface an HI5741 to the hsp45106. definition of specifications integral linearity error (inl) is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. differential linearity error (dnl) is the measure of the error in step size between adjacent codes along the converter?s transfer curve. ideally, the step si ze is 1 lsb from one code to the next, and the deviation from 1 lsb is known as dnl. a dnl specification of greater than -1 lsb guarantees monotonicity. feedthru is the measure of the und esirable switching noise coupled to the output. output voltage full scale settling time is the time required from the 50% point on the clock input for a full scale step to settle within an 1 / 2 lsb error band. output voltage small scale settling time is the time required from the 50% point on the clock input for a 100mv step to settle within an 1 / 2 lsb error band. this is used by applications reconstructing highly correlated signals such as sine waves with more th an 5 points per cycle. glitch area (ge) is the switching transient appearing on the output during a code transition. it is measured as the area under the curve and expressed as a volt ? time specification (typically pv-s). differential gain ( ? a v ) is the gain error from an ideal sine wave with a normalized amplitude. differential phase ( ? ) is the phase error from an ideal sine wave. (21) i out 100mhz low pass filter scope HI5741 64 ? 50 ? figure 24. glitch test circuit figure 25. measuring glitch energy a (mv) t (ns) glitch energy = ( a x t )/2 HI5741 ref out i out 1 / 2 ca2904 + - + - + - 50 ? 5k ? 1 / 2 ca2904 5k ? 60 ? 240 ? 240 ? hfa1100 v out 0.1 f figure 26. bipolar output configuration (21) (26) HI5741
12 fn4071.12 september 20, 2006 signal to noise ratio (snr) is the ratio of a fundamental to the noise floor of the analog output. the first 5 harmonics are ignored, and an output filter of 1 / 2 the clock frequency is used to eliminate alias products. total harmonic distortion (thd) is the ratio of the dac output fundamental to the rms sum of the harmonics. the first 5 harmonics are included, and an output filter of 1 / 2 the clock frequency is used to eliminate alias products. spurious free dynamic range (sfdr) is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. a sine wave is loaded into the d/a and the output filtered at 1 / 2 the clock frequency to eliminate noise from clocking alias terms. multi-tone power ratio (mtpr) is the amplitude difference from peak amplitude to peak di stortion (either harmonic or non-harmonic). an 8 tone pattern is loaded into the d/a. the tone spacing of this pattern ( ? f) is created such that tones 1 through 4 and 5 through 8 are spaced equally, with tones 4 and 5 spaced at 2 ? f. mtpr is measured as the dynamic range from peak power to peak distortion in the 2 ? f gap. intermodulation di stortion (imd) is the measure of the sum and difference products produced when a two tone input is driven into the d/a. the distortion products created will arise at sum and difference frequencies of the two tones. imd can be calculated using the following equation: imd 20log (rms of sum and difference distortion products) rms amplitude of the fundamental () ------------------------------------------------------------------------------------------------------------------------------- ----------------------- - = encoder controller baseband bit stream k9 c11 b11 33 msps clk clk mod2 mod1 hsp45106 sin15 r 4 50 1 2 3 4 5 6 7 8 9 10 15 28 17 18 u2 d13 (msb) d12 d11 d10 d9 d8 d7 d6 d5 d4 dv cc v cc 16 u1 clk dgnd HI5741 dv ee dgnd -5.2v_d av ee av ss i out i out / c amp out c amp in r set aret ref out 21 20 24 25 26 23 19 27 22 r 1 64 r 2 64 r 3 976 c 2 0.1 f c 1 0.01 f -5.2v_a -5.2v_a filter to rf up-convert stage l 2 10 h l 1 10 h -5.2v_a -5.2v_d c10 mod0 a11 f10 f9 f11 h11 g11 g9 j11 g10 d10 j10 k11 b8 b6 b7 a7 c7 c6 a6 a5 c5 a4 b4 a3 a2 b3 a1 b10 b9 a10 e11 e9 h10 k2 j2 a8 v cc v cc v cc pmsel enporeg enofreg encfreg enphac entireg inhofr initpac inittac test parser binfmt c15_msb c4 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 a2 a1 a0 cs wr paci oes oec dacstrb sin14 sin13 sin12 sin11 sin10 sin9 sin8 sin7 sin6 sin5 sin4 sin3 sin2 sin1 sin0 l1 k3 l2 l3 l4 j5 k5 l5 k6 j6 j7 l7 l6 l8 k8 l9 l10 cos15 cos14 cos13 cos12 cos11 cos10 cos9 cos8 cos7 cos6 cos5 cos4 cos3 cos2 cos1 cos0 tico c2 b1 c1 d1 e3 e2 e1 f2 f3 g3 g1 g2 h1 h2 j1 k1 b2 11 12 d3 d2 -5.2v_a 13 14 d1 d0 (lsb) figure 27. psk modulator using the HI5741 and hsp45106 16-bit nco HI5741
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn4071.12 september 20, 2006 HI5741 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93

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